[ArXiv 2026] Heron vs. Eagle: Mapping the Real-World Quantum Advantage of IBM’s Next-Gen Processors
Benchmarking Quantum Computers via Protocols, Comparing IBM's Heron vs IBM's Eagle
This paper presents a protocol-based benchmarking study comparing two generations of IBM quantum processors: the Eagle-r3 (Brisbane) and the Heron-r2 (Kingston). By utilizing a hierarchy of quantum protocols ranging from "Do-nothing" to "Entanglement Swapping," the authors evaluate the practical quantum advantage of specific sub-chips and demonstrate that the newer Heron architecture significantly outperforms the Eagle generation in scalability and operational fidelity.
TL;DR
Not all qubits are created equal. This latest benchmarking study from Technion University moves beyond simple gate-fidelity metrics to evaluate quantum computers at the protocol level. By pitting IBM’s new Heron-r2 (Kingston) against the older Eagle-r3 (Brisbane), the researchers reveal that while the previous generation struggled with basic entanglement, the Heron architecture marks a significant leap in regional reliability and multi-qubit scalability.
The "Quantumness" Gap: Why Traditional Benchmarking Isn't Enough
In the race for quantum supremacy, we often focus on qubit counts (127 qubits! 156 qubits!). However, raw numbers are deceptive if the hardware cannot successfully execute a simple teleportation or entanglement swap across its physical fabric.
The authors argue that existing methods like Randomized Benchmarking provide a "gate-level" view that masks system-wide failures. Their solution? Protocol-based Benchmarking. If a sub-segment of a chip cannot pass a "Do-nothing" test or a "Transmit" test (the most basic movement of quantum information), it essentially lacks a "quantum advantage" for practical computation.
Methodology: The Optimal Lookup Workflow
The researchers developed a rigorous, budget-efficient funnel called the Optimal Lookup Workflow. Instead of testing the whole chip at once, they treat the chip as a collection of "sub-chips" (typically 12-qubit rectangles).
- c2c (Corner-to-Corner): A quick "first impression" of connectivity.
- M-L (Maximal Length): Testing paths that span the extent of the rectangle.
- A-L (All Lengths): The "Heavy Duty" test—running every possible inner path protocol to prove a sub-chip's total capability.
Figure 1: The Optimal Lookup Workflow funnel for identifying high-performance sub-chips.
Heron vs. Eagle: A Generation Apart
The results confirm what many suspected: the Heron architecture is a game-changer for IBM.
- The Brisbane (Eagle) Struggle: Even after IBM "modified" the Brisbane chip in late 2025, it failed to produce a single pair of rectangles capable of passing the "Do-nothing" or "Teleportation" protocols. Its Protocol Vector (a visualization of sub-chip health) showed vast "red zones" where quantum information simply decayed too fast.
- The Kingston (Heron) Triumph: Kingston demonstrated remarkable resilience. It didn't just pass protocols in single rectangles; it maintained performance when those rectangles were paired. This suggests that Heron’s cross-rectangle communication is significantly more robust.
Figure 2: The Protocol Vector for Brisbane. Note the limited "quantumness" across the chip map.
Figure 3: The Protocol Vector for Kingston showing much higher protocol viability across more sub-chips.
Critical Insight: The Fidelity Plateau
One of the most profound findings in the Kingston (Heron) data is the Fidelity Plateau. In many protocols, as the "Swap Distance" (the number of gates needed to move a state) increased, the fidelity did not continue to drop linearly to zero. Instead, it stabilized. This stabilization is the "holy grail" for scaling quantum algorithms, as it allows for longer-range interactions without total loss of signal.
Summary Table: Quantitative Superiority
| Protocol | Kingston (Successful Rectangles) | Brisbane (Successful Rectangles) |
|---|---|---|
| Transmit | 13 | 10 |
| Teleportation | 11 | 4 |
| Bell-State Transfer | 12 | 1 |
| Super-Dense Coding | 9 | 0 |
| Entanglement Swapping | 10 | 0 |
Conclusions & Future Outlook
This paper serves as both a warning and a guide. For users, it highlights the necessity of Hardware Selective Programming—choosing specific "sub-chip" clusters based on real-time protocol vectors. For the industry, it proves that architectural improvements in the Heron generation (better qubit isolation and gate control) are translating into measurable, larger-scale quantum capabilities.
However, the Temporal Consistency issue remains a hurdle. Even Kingston showed performance drifts over week-long intervals. The future of quantum computing may not just lie in better qubits, but in better real-time Quality Assurance (QA) systems that update these Protocol Vectors daily.
