The question behind the detector readout problem
Future particle physics colliders are expected to run at a 40 MHz event rate with pixel detectors comprising billions of readout channels, and radiation damage progressively shifts how those detectors respond. Central processing is not an option at those rates, so the classifier has to sit on the chip, inside tight space and power budgets, and still be updatable after deployment.
The paper asks whether logic neural networks fit that role. Instead of multiply-accumulate arithmetic and nonlinear activations, LNNs learn Boolean functions such as AND and XOR, or lookup tables, which map directly onto digital circuits. The authors evaluate dense QKeras, dense LNN, and convolutional LNN classifiers on the public SmartPixels benchmark, comparing classification performance, post-synthesis FPGA resource use, robustness to random bit flips, and a new reconfigurability mechanism.
How a trained LNN becomes a digital circuit
All LNNs in this study use only 2-input lookup tables, described as logic gates, with random fixed connectivity. Inputs are binarized by distributive thresholding into 100 ordered thresholds per feature. During training each gate is a softmax-weighted sum over all 16 two-input Boolean functions, evaluated with fuzzy logic so it stays differentiable; at inference the softmax is replaced by its argmax, producing a discrete circuit.
The dense models take 14 high-level input features, while the convolutional models use a 13x8 time profile plus one high-level feature. Hardware cost is estimated by FPGA synthesis on a Xilinx VU13P with a requested 4.1667 ns clock period, about 240 MHz, with DSP blocks disabled and the combined LUT plus flip-flop count used as the logic-resource proxy. Input preprocessing, I/O and routing, and downstream decision logic are excluded, and place-and-route and timing closure are left to future work.
Roughly 19x less logic at matched accuracy
At comparable balanced accuracy, 0.807 for the dense LNN and 0.798 for QKeras, the dense LNN required 14,418 LUTs plus flip-flops against 275,815 for QKeras, about 19x lower resource utilization. Across the architecture sweep, dense LNNs exceeded 0.81 balanced accuracy while staying in the tens-of-thousands resource regime.
The efficiency gain matters most for the time-resolved representation. Earlier SmartPixels work found that an eight-profile convolutional model improved performance over a dense single-profile model but raised the parameter count by roughly 36x, and that convolutional architecture was not carried into the hardware implementation. Here the convolutional LNN uses the same 105-input, eight-profile representation, needs post-synthesis resources comparable to the dense LNNs, and reaches balanced accuracies above 0.84.
Bit-flip robustness depends on the input encoding
Faults are injected into each model's own digital input representation: 1,400 threshold-encoded bits for the LNN and 112 bits from the 8-bit representation of the 14 QKeras inputs. The reported fault rate is therefore the fraction of corrupted bits within each model's own encoding, not a shared physical dose, and each nonzero point is averaged over five independent full-test realizations.
Comparing models with similar fault-free balanced accuracy, 0.807 for the LNN and 0.798 for QKeras, the LNN degrades substantially more slowly. At about 10% input corruption, models trained without faults fall to roughly 47% and 36% balanced accuracy for LNN and QKeras respectively; with fault-aware training they retain roughly 72% and 46%. Fault-aware training helps both architectures, but the LNN keeps a pronounced advantage under this fault model.
Why retraining an LNN is not just rewriting registers
For conventional arithmetic models, retraining after deployment is simple: the computational graph is fixed and only the trained parameters in writable registers change. LNNs do not separate cleanly that way. Much of their efficiency comes from compactifying the Boolean graph at compile time, folding constants and merging redundant gates, so the surviving topology is itself a function of the trained truth tables. Retraining can change connectivity, not merely stored coefficients.
The proposed mechanism keeps a designated subset of gates with fixed two-input connectivity but reads their four-entry truth table from a small runtime configuration register. Each such gate becomes a multiplexer with two select bits and four configuration bits stored in flip-flops, while all remaining gates stay permanently fixed. The cost has a direct part, the multiplexer and register logic, and an indirect part, the loss of compactification because a reconfigurable gate can no longer be folded away.
Three reconfigurable layers retain 99% of retrained accuracy
Reconfigurability is evaluated on the dense LNN trained on the non-irradiated SmartPixels sample and retrained on samples at two accumulated fluences, low and high. This dataset differs slightly from the one used for the efficiency and bit-flip studies, so absolute numbers are not directly comparable across those sections.
The fully static model degrades on drifted data, while unrestricted retraining restores baseline performance. Making every gate reconfigurable raises resource usage roughly 17-fold relative to the static model. The oracle that knows the retrained model in advance performs best among retrained models of comparable size. Selecting the reconfigurable subset on one irradiation scenario and applying it to the other gave no advantage over assuming no knowledge of the drift at all. The no-knowledge approach performed surprisingly well: with three reconfigurable layers it retained 99% of fully retrained accuracy at 37% of the resource cost of full reconfigurability, and making whole layers reconfigurable Pareto-dominated the gate-wise criteria.
FPGA synthesis is a proxy, not a chip
The hardware results use FPGA synthesis as a surrogate for on-chip implementation cost. ASIC synthesis, place-and-route, and power analysis are still needed for realistic deployment estimates, and a first system-on-chip integrating an LNN on an eFPGA is targeted for tape-out in 2027. The robustness study covers input bit flips only and should be extended to faults in intermediate activations and to convolutional LNNs, and reconfigurability is evaluated only for dense models.
Further optimization is possible by learning the connectivity or the binarization thresholds; the authors note that learning thresholds could improve bit-efficiency once data I/O cost is included. These are stated as future directions rather than demonstrated results.
Reconfigurability should be spent on whole layers
The decision-relevant comparison in this paper is not LNN versus arithmetic networks in the abstract, but how a fixed reconfigurability budget should be allocated. Under the evaluated drift scenarios, making whole layers reconfigurable was the better use of resources than selecting individual gates, and the no-knowledge layer-wise strategy matched the best partial-knowledge alternative while retaining 99% of fully retrained accuracy at 37% of full reconfigurability cost.
That makes layer-level reconfigurability the priority to test first for a detector readout classifier, with the caveat that the claim rests on FPGA synthesis estimates and on dense LNNs retrained at two accumulated fluences. The efficiency and bit-flip results support LNNs as a candidate architecture; the reconfigurability result says where to place the flexibility if the architecture is adopted.
Sources used in this answer
Reconfigurable On-Chip AI for Particle Physics Detectors with Logic Neural Networks
Dense LNNs matched quantized QKeras accuracy with about 19x lower post-synthesis FPGA logic use, degraded more slowly under random input bit flips, and a three-layer reconfigurable design retained 99% of fully retrained accuracy at 37% of full reconfigurability cost.