Fast Feedthrough Logic: Revolutionizing GaAs Logic with Partial Evaluation

TL;DR

The paper introduces Feedthrough Logic (FTL), a novel dynamic logic family for Gallium Arsenide (GaAs) that breaks the speed barriers of traditional domino logic. By allowing gates to begin evaluating before inputs are valid and resetting outputs to "low," FTL eliminates classic issues like charge sharing and leakage. The result? A 4-bit adder that is 11 times faster than 0.18-μm CMOS and consumes significantly less power.

Background: The GaAs Bottleneck

Gallium Arsenide (GaAs) has always promised superior electron mobility compared to Silicon, but its implementation in VLSI has been hampered by the limitations of dynamic logic. Previous "domino" designs precharged outputs to "high," leading to:

• Charge Redistribution: Unwanted sharing of charge between nodes.
• Leakage Current: Difficulty maintaining the "high" state in GaAs MESFETs.
• Area Overhead: The mandatory use of inverters between stages to maintain logic polarity.

FTL flips this script by resetting to low, turning these disadvantages into a high-speed advantage.

Methodology: The Magic of "Feedthrough Evaluation"

The core innovation of FTL lies in its "Feedthrough Evaluation" concept. Unlike standard logic where a signal must travel from $V_{SS}$ to $V_{DD}$, FTL gates are "primed."

1. Reset Phase: When the clock is high, the output is pulled to ground.
2. Evaluation Phase: When the clock goes low, the output starts rising toward a switching threshold ($V_{TH}$).
3. Partial Transition: Because the gate is already at an intermediate voltage, when the input finally arrives, the output only needs a small "nudge" to reach its final high or low state.

Figure 1: (a) Basic FTL Gate, (b) Differential FTL, and (c) Cascaded chain illustrating the feedthrough concept.

This partial swing is the secret sauce. As shown in the paper's mathematical derivation, the propagation delay ($t_P$) is directly proportional to the voltage swing. By reducing the required swing, FTL achieves a massive speedup.

Experimental Results: SOTA Performance

The authors put FTL to the test by designing a 4-bit Ripple Carry Adder. The results were compared against dozens of other logic families and standard CMOS.

Performance Comparison:

• Speed: The FTL adder achieved a delay of 172 ps.
• Frequency: Stable operation up to 2.0 GHz.
• Power: Consumed only 1.3 mW, nearly half of what a comparable 0.18-μm CMOS circuit would use for the same task.

Table II: FTL vs. other GaAs logic families and CMOS. Note the "Figure of Merit" (Γ) where FTL outperforms its nearest GaAs competitor by 7000x.

Pipelining with the Single-Phase Latch (SPL)

To keep up with the logic’s speed, the authors developed a Single-Phase Latch (SPL). Most dynamic pipelines struggle with "clock skew" (where clock signals don't arrive at the same time). Because SPL and the preceding FTL logic use the same clock phase, the race condition is naturally eliminated. This latch is incredibly compact, using only 6 transistors—half that of traditional DCFL latches.

Critical Insight: Why it Works

The "Aha!" moment of this paper is the realization that in high-speed GaAs, we don't need a full rail-to-rail swing for every gate in a chain. By treating the logic chain as a continuous wave of partial evaluations, the authors effectively increased the "bandwidth" of the digital signal path.

Conclusion & Limitations

FTL is an elegant solution for high-performance arithmetic units. However, there are trade-offs:

• Area: While FTL is more compact than other GaAs families, it still takes up significantly more area than CMOS ($37imes$ in this study).
• Frequency Bounds: Like all dynamic logic, it has a lower frequency limit (approx. 125 MHz) due to charge leakage—it cannot sit idle.

For high-frequency ASICs in communication or signal processing (like the 11-tap FIR filter demonstrated in the paper), FTL represents a significant leap forward in the GaAs design space.